Hardware Description Language or HDL is a specialized computer language used to describe the structure, design and operation of electronic circuits. In general, Hardware Description Language enables precise, formal descriptions of electronic circuits, and is used to automate analysis, simulation, and simulated testing of an electronic circuit. For example, Hardware Description Language is often used to simulate complex circuits such as microprocessors.
Hardware Description Language can be functionally simulated in software. Functional simulation is the use of a computer program to simulate the execution of a second computer program written in a language other than binary machine code. For example, FIG. 1A illustrates a model for functionally simulating HDL designs. According to the model of FIG. 1A, a programmer develops an HDL design 100 to describe an electronic circuit. Using an HDL compiler 101, the HDL design 100 is compiled as a compiled design 102. An HDL simulator 103 is used to simulate the compiled design 102. Simulation of the compiled design 102 is necessary to verify that the HDL design 100 actually performs as intended. Simulation is performed using various software that facilitates a testbench environment. During simulation, a stimulus or input is provided to the compiled design 102 and simulation results 104 are obtained.
Hardware Description Language can also be emulated. While functional simulation relates to the simulating of non-binary machine code, software emulation relates to the simulation of execution of binary machine code. FIG. 1B illustrates a synthesized emulation usage model for emulating HDL designs. According to the model of FIG. 1B, a programmer develops an HDL design 120 to describe an electronic circuit. Using an HDL synthesizer 121, the HDL design 120 is synthesized as a synthesized design 122. An HDL emulator 123 is used to emulate the synthesized design 122. As with the functional simulation model of FIG. 1A, a stimulus or input is provided to the synthesized design 122 and simulation results 124 are obtained.
The models of FIGS. 1A and 1B may be combined in a co-simulation usage model, as illustrated in FIG. 1C, which increases the efficiency of the overall simulation process. In this model, an HDL design 140 is converted into an HDL design 141 that is suitable for emulation and an HDL testbench 147 that is suitable for simulation. The HDL design 141 is subjected to an HDL synthesizer 142 to yield a synthesized design 143. The HDL testbench 147 is subjected to an HDL compiler 148 to yield a compiled testbench 149. The synthesized design 143 is emulated by emulator 144 while the compiled testbench 149 is simulated using HDL simulator 150. The parallel processes of emulation and simulation are linked via a CoSim link 146 which shares information between the two processes, improving the speed of the combined processes. Simulation results 145, 151 are generated from the parallel processes.
Even the co-simulation usage model, however, results in processing inefficiencies. Simulating Hardware Description Language can be problematic, especially on modern PC hardware based on x86 server architectures. In such architectures, Hardware Description Language simulation can be inefficient due to a significant amount of overhead in the representation of the semantic operations of an HDL simulation in the native language. Additionally, inefficiencies arise from managing the processing of the HDL simulation kernel in software. As a result, HDL simulation can be expensive in terms of processor time.
There are many specific reasons for why HDL simulation is slow, especially in x86 server architectures. One reason is that in x86 server architectures, the representation of HDL logical simulation semantics is large, resulting in large bandwidth requirements. Another reason is that cache memory is underutilized due to an abundance of non-repeated actions during, for example, a Verilog simulation. The inability to effectively utilize a memory cache results in slower performance. Another reason for slowness is poor bus effective utilization in an x86 architecture, due to the fixed size of cache lines. Thus, significant mismatches between the number of bytes used and the number of bytes read mean that buses are inefficiently utilized. Additionally, software simulation kernel events and/or scheduling operations are typically not cached well as the ratio of design size to kernel size exceeds 1 M to 1.
Therefore, there is a desire to improve and correct the inefficiencies resulting from HDL simulation.